Fixed frequency and modulated signals are commonly needed in electronic and communication systems. A variety of methods are employed for generation of such signals, including phase locked loops (PLL) and direct digital synthesis (DDS) and many variations upon these methods.
A typical PLL system, shown in FIG. 1, will use a voltage controlled oscillator (VCO), feedback divider, phase detector, loop filter, and reference clock to generate a constant frequency signal. This system is agile in that the output frequency can be programmed in discrete steps by changing the reference divider and the feedback divider. The limitation of this approach is that only discrete frequency steps are available, the size of the steps being a function of the range of the reference and feedback divider.
Many variations of the basic PLL architecture are well known that improve on frequency resolution and spectral purity including fractional-N frequency synthesis and multiple-loop approaches.
A typical DDS system, shown in FIG. 2, will use a fixed reference clock, a phase accumulator, sine look-up table, digital to analog converter, and smoothing filter to generate a constant frequency signal. This system is also agile, with the frequency steps being a function of the length of the phase accumulator register and the reference clock. Generally, a DDS approach offers fine resolution in setting the output frequency. There are many variations on this approach, including mechanisms to increase spectral purity.
Direct digital synthesizers are described by Crawford, J. A., Frequency Synthesizer Design Handbook, Artech House, Inc. Norwood Mass. 1994. This reference also provides some treatment of the issues in DDS design.
An advantage of the DDS frequency generation over the PLL approach is that the DDS is mostly digital, offers improved frequency resolution, and avoids the stability issues of the PLL.
Referring again to FIG. 2, reference clock 10 causes phase accumulation register 20 to latch the value of summer 30 which adds a phase increment value 26 to the previous output value of phase accumulation register 20. In this manner, each reference clock period causes the phase value output by the phase accumulation register 20 to increase linearly, creating a phase ramp. The rate of increase in the phase accumulator value is determined by the phase increment value. The phase accumulator value will increase until the maximum value is reached, then the value will rollover to the minimum value, thus a sawtooth shaped waveform is produced, as shown in waveform A of FIG. 3. The function combining a summer, phase accumulation register and phase increment value is commonly referred to as a numerically controlled oscillator (NCO).
Phase increment 26 is computed using the following formula:
______________________________________ Pinc = 2 N * Fout/Fref ______________________________________
were:
Pinc is the phase increment value applied to the NCO,
N is the number of bits in the phase accumulation register,
Fout is the desired output frequency,
Fref is the reference frequency.
The phase accumulator value is applied to sine wave lookup table 40 which converts the phase value to an amplitude value. This sine wave lookup table is generally implemented using a read only memory (ROM) which stores the sine trigonometric function. A phase value applied of X is translated to an amplitude value sine(X). Lookup table 40 maps the full scale of the phase value output by the NCO to one cycle of a sine wave. As the phase value increases from 0 to full scale, one sine wave cycle will be generated.
In order to provide fine frequency resolution, the phase accumulation register 20 is set to a large value, such as 32 or 48 bits. The entire phase accumulation register output is not applied to the sine mapping table, instead only a few of the most significant bits are applied, typically 8 to 14 bits. With each additional bit applied to the sine lookup table the number of memory locations doubles. The number of bits is limited by practical consideration of the size of the lookup table.
Additionally, the number of bits of output from the lookup table is similarly limited, typically 8 to 12 bits. A compromise is made between complexity and cost of the lookup table and the degradation of the signal generated. The existence of the sine lookup table and the compromise resulting from truncation of the input and output precision are significant design issues in a DDS system.
The output of the lookup table, which represents discrete amplitude levels of the desired sine wave, is applied to a digital to analog converter 50 (DAC). The voltage output of the DAC changes in discrete steps based on the digital value supplied by the lookup table, as shown in waveform B of FIG. 3. Generally such steps are undesirable because they contain the high frequency content of the reference clock. A smoothing filter 60 is used to attenuate the high frequency content and result in smooth transition between steps, as shown in waveform C of FIG. 3. The signal is relatively pure spectrally, since the time domain waveform is sinusoidal and thus contains a fundamental and no harmonics.
The basic DDS system generates a sinusoidal waveform. Often a square wave signal is desired, for example when driving digital logic. In this case a hard limiter 70 is used to square the signal and generate the appropriate high and low logic levels. The hard limiter changes state when the sine wave crosses the threshold level. With the threshold set at the zero level, a high level is output when the sine wave is above the threshold, and a low logic is output then the sine wave is below the threshold. The square wave thus changes level at the zero crossing in the sine wave, as shown in waveform D of FIG. 3.
Although the final signal generated is a digital square wave with only two amplitude levels, the phase accumulator output must be processed by the sine lookup table, smoothing filter, and hard limiter to obtain acceptable square wave properties. The smoothing filter acts to interpolate the zero crossing point between discrete amplitude levels generated by the sine lookup table. The square wave thus can have a constant period and good symmetry that are not available when using the signals directly from the phase accumulator.
The sawtooth wave from the phase accumulator cannot be used directly because the period modulates due to the finite precision of the phase increment and discrete nature of the phase steps. The zero crossings do not occur at fixed intervals, instead they vary between two intervals of K and K+1, where K is an integer multiple of the reference clock period. If the smoothing filter is applied to the phase, the zero crossing in the positive direction is interpolated, but the time of the zero crossing in the negative direction is not interpolated because the slope is vertical due to the discontinuity as the phase accumulator rolls over.
The use of a sine lookup table in conventional DDS systems increases cost, power, and size. Much effort has been directed towards making sine lookup tables more efficient. One example is disclosed in U.S. Pat. No. 4,486,846 to McCallister et al (1984) which describes using quadrant replication for reducing the memory storage requirements. U.S. Pat. No. 4,905,177 to Weaver et al (1990) describes an efficient manner of converting phase to sine amplitude.
U.S. Pat. No. 3,882,403 to Gerken (1975) describes a digital frequency synthesizer without a sine lookup table but has the disadvantage of requiring a voltage controlled oscillator and multiple DACs.
U.S. Pat. No. 4,328,554 to Mantione (1982) describes a frequency synthesizer without a sine lookup table. An NCO architecture is used, with the MSB of the NCO driving an up/down counter to generate a triangle wave shape which is then shaped to a sine wave. This system results in a sine wave. Although not disclosed in Mantione, the sine wave which could then be converted to a square wave using a hard limiter. The first disadvantage of this approach is the complexity of two stages of conversion: phase to triangle conversion then triangle to sine conversion. Another disadvantage is the use of only the MSB of the phase accumulator to generate the triangle wave, since the period of the MSB had period modulation as described above. Another disadvantage is the use of an up/down counter for triangle wave conversion since this counter divides down the NCO frequency and thus limits the highest frequency of operation. Another disadvantage is the imprecision of the diode clipping sine shaper.
Since the amplitude information contained in the sine lookup table is removed when the DDS system is generating a square wave, it is wasted. The harmonic purity of a sinusoidal waveform at an intermediary stage is not needed since the final square wave necessarily contains odd harmonics. Simple elimination of the sine lookup table results in unacceptable square wave properties, specifically the period will be modulated. A more efficient approach to generating square waves with a DDS is needed that avoids a sine lookup table.